Specification

Implement a D flip-flop with enable and active-high asynchronous reset. The flip-flop stores i_d on the rising edge only if i_en is active.

Implement a 4-bit serial shift register (SISO) with asynchronous reset. Bits shift right on each rising edge.

Implement a Mealy state machine that detects the binary sequence «101» on a serial input, with overlap handling.

Implement a combinational ALU performing 4 operations on two 8-bit operands: addition, subtraction, AND, and OR, with carry flag.

Implement a transparent latch to understand this classic FPGA pitfall. When enable is high, output follows input; when enable is low, output holds its value.

Implement an 8-bit loadable shift register combining parallel load and left shift, with load taking priority.

Implement a pulse stretcher that extends a single-cycle signal into an output active for G_CYCLES clock cycles.

Implement a safety watchdog timer: a counter decrements continuously and triggers a timeout if no i_kick signal is received in time.

Implement a 3-state FSM controller (OFF, BLINK, ON) that drives an LED with blinking. Each button press advances the sequence.

Implement a PWM generator with a sequential counter and a combinational output controlled by the duty cycle.

Implement an 8-bit Linear Feedback Shift Register (LFSR) with seed loading and combinational feedback output.

Implement a 4-sample moving average filter with a sequential shift register and combinational average computation.

Implement an N-bit parallel register with enable and combinational update detection.

Implement a two flip-flop CDC synchronizer with combinational rising and falling edge detection.

Implement a synchronous CRC-16 calculator, bit by bit, with the CCITT polynomial and a combinational output of the CRC register.

Implement the first two phases of an I2C master: START condition and sending the 7-bit address + R/W bit via a 5-state FSM.

Implement a 7-segment decoder that converts a BCD digit (0-9) into 7 signals to light the correct display segments, with enable.

Implement a top level that instantiates a BCD counter and a 7-segment decoder, correctly wiring internal signals and external ports.

Design a 1-bit full adder with carry-in and carry-out. This block is the fundamental building block of any arithmetic unit.

Design a purely combinational 4-to-1 multiplexer. The 2-bit selector chooses which of the 4 inputs is forwarded to the output.

Design a 2-to-4 binary decoder with an enable signal. The output is a one-hot code corresponding to the selector value when the decoder is active.

Design an 8-bit parity checker. The output indicates whether the number of 1-bits in the input is odd (parity = 1) or even (parity = 0).

Design a 4-bit combinational comparator that compares two unsigned numbers and indicates whether the first is greater than, equal to, or less than the second.

Design a 4-bit combinational multiplier that computes the product of two unsigned numbers on an 8-bit output.

Design a combinational converter that transforms an 8-bit BCD (Binary-Coded Decimal) number into its 7-bit binary value.

Design a two-input AND logic gate. This is the fundamental building block of all combinational logic.

Design a two-input OR logic gate. The output is active when at least one input is '1'.

Design a logic inverter. The output is the complement of the input.

Design a two-input NAND logic gate. This is the universal gate: any logic function can be built using NAND gates.

Design a two-input NOR logic gate. Like NAND, it is a universal gate.

Design a two-input XOR (exclusive OR) logic gate. Used in adders, parity detection and encryption.

Design a two-input XNOR (equivalence) logic gate. The output is active when both inputs are the same.

Design a purely combinational 2-to-1 multiplexer. The selector chooses which of the 2 inputs is forwarded to the output.

Design a purely combinational 8-to-1 multiplexer. The 3-bit selector chooses which of the 8 inputs is forwarded to the output.

Design a 1-to-2 demultiplexer. The input is routed to one of the two outputs based on the selector.

Design a 1-to-4 demultiplexer. The input is routed to one of the four outputs based on the 2-bit selector.

Design a 3-to-8 binary decoder with enable signal. The output is a one-hot code corresponding to the selector value.

Design a 4-bit binary to Gray code converter. Gray code is used in communications because only one bit changes between consecutive values.

Design a 4-bit Gray code to binary converter. Inverse operation of the binary to Gray converter.

Design a half adder that adds two bits without carry-in.

Design a 4-bit combinational subtractor that computes the difference of two unsigned numbers with borrow indication.

Implement a JK flip-flop with active-high asynchronous reset. The JK flip-flop is the most versatile: it can hold, set, reset, or toggle its output.

Implement a T (Toggle) flip-flop with active-high asynchronous reset. When T='1', the output toggles on each rising edge.

Implement a synchronous SR flip-flop with active-high asynchronous reset. S sets the output to '1', R resets it to '0'.

Implement a 4-bit register with enable and active-high asynchronous reset.

Implement a 4-bit left shift register with serial input and asynchronous reset.

Implement a 4-bit serial-in parallel-out (SIPO) shift register with asynchronous reset. Bits enter serially and are available in parallel.

Implement a 4-bit synchronous up counter with enable and asynchronous reset.

Implement a 4-bit synchronous down counter with enable and asynchronous reset. Reset initializes to maximum value (15).

Implement a 4-bit ring counter with asynchronous reset. A single '1' bit circulates through the register.

Design a combinational encoder that converts a valid BCD digit to Excess-3 code.

Encode 4 data bits with three even-parity bits to form a Hamming (7,4) word.

Implement an N-bit ripple carry adder using only logical operators, without any arithmetic library.

Implement a generic bidirectional counter with parallel load, enable, and asynchronous reset.

Implement a debouncer circuit with configurable stabilization time via generics.

Implement an 8-to-3 combinational priority encoder that encodes the position of the highest-priority active bit.

Implement a 4-bit Johnson counter with synchronous reset. The counter goes through a sequence of 8 states before returning to its initial state.

Implement an 8-bit barrel shifter performing a logical left shift in 3 combinational stages (shift-by-4, shift-by-2, shift-by-1).

Implement a W1C register: bits are set via i_set_en and cleared by writing 1 via i_clr_en.

Generate a 1µs periodic pulse from a system clock with known period.

Implement a generic synchronous N-bit counter with enable, asynchronous reset and overflow indication.

Implement an 8-bit combinational comparator that compares two unsigned numbers and indicates their relationship.

Implement a 4-bit combinational block selectable between addition and subtraction via a control signal.

Implement a generic cascadable comparator with cascade inputs for connecting multiple stages.

Implement an 8-bit register with parallel load enable and asynchronous reset.

Implement a 4-bit shift register that can shift left, shift right, parallel load, or hold its value.

Implement an 8-word by 4-bit read-only memory (ROM), purely combinational.

Implement a 16-word by 4-bit ROM using a VHDL constant array.

Implement an 8-word by 4-bit RAM with synchronous write and asynchronous read.

Implement a 16-word by 4-bit RAM with synchronous write and asynchronous read.

Implement an 8-deep, 8-bit LIFO stack with push, pop, and empty/full flags.

Implement an 8-word by 8-bit dual-port RAM: independent write and read ports.

Implement a 4-register, 8-bit register file with 1 write port and 2 read ports.

Implement a 4-bit Carry Lookahead Adder (CLA).

Implement an 8-bit CLA adder by cascading two 4-bit CLA blocks.

Implement a 4-bit, 2-stage barrel shifter that can logically shift left by 0 to 3 positions.

Implement an adder for a simplified float format: 1 sign bit, 3 exponent bits (bias 3), 4 mantissa bits (implicit 1.xxxx).

Implement a multiplier for the same simplified float format: 1 sign bit, 3 exponent bits (bias 3), 4 mantissa bits (implicit 1).

Implement an even parity generator: generates a parity bit for 7 data bits, and verifies an 8-bit word (7 data + 1 parity).

Implement a population counter: count the number of '1' bits in an 8-bit vector.

Implement a priority multiplexer: 4 data channels of 4 bits with request bits. The highest-priority active channel is selected.

Implement a 4-phase handshake synchronizer to transfer a data bus between two independent clock domains.

Implement a 5-tap direct-form FIR low-pass filter with line buffer and fixed coefficients.

Transform a 5x5 combinational multiplier into a 4-stage pipelined architecture.

Decode a Hamming (7,4) word, compute the syndrome and correct one single-bit error.

Implement a Parallel-In Serial-Out register with parallel load and controlled shifting.

Design a synchronous counter that cycles through states 0 to 5 with enable and terminal-count pulse.

Implement an interrupt generator: each IT vector stays active for g_MIN_WIDTH_PULSE cycles then is reported in the status register.

Implement a generic AXI4-Lite master capable of performing read and write accesses on an AXI4-Lite bus.

Implement a generic AXI4-Lite slave with simplified register interface.

Implement a simple AXI4 master managing the three write channels: Write Address (AW), Write Data (W) and Write Response (B).

Implement a 16-bit accumulator-based mini processor: ALU, PC/IR/ACC/R registers, control FSM, and top-level assembly. 14 instructions covered.

Implement a hardware SHA-256 core on a 512-bit block: logical functions, message schedule shift register, compression unit and top-level FSM.

Implement a successive-approximation conversion FSMD to drive an internal DAC and read a comparator.