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Chargement…
The module exposes three 32-bit registers accessible via AXI4-Lite: REG_CTRL (0x00), REG_PERIOD (0x04), REG_GAIN (0x08). Two independent state machines handle write and read transactions per the AXI4-Lite protocol.
Generics:
g_BASE_ADDR : std_logic_vector(31 downto 0) - Base address (default x"0000_0000")AXI-Lite Ports:
i_axi_aclki_axi_aresets_axi_awaddrs_axi_awvalids_axi_awreadys_axi_wdatas_axi_wstrbs_axi_wvalids_axi_wreadys_axi_bresps_axi_bvalids_axi_breadys_axi_araddrs_axi_arvalids_axi_arreadys_axi_rdatas_axi_rresps_axi_rvalids_axi_rreadyRegister Ports:
o_reg_ctrl | Output | 32 bits | REG_CTRL value |
|---|---|---|---|
o_reg_period | Output | 32 bits | REG_PERIOD value |
o_reg_gain | Output | 32 bits | REG_GAIN value |