AXI4 Master - Read Channels

Intermediate

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Specification

01General Operation

AXI4 single-beat read master. The rising edge of i_read_go starts a transaction at address i_rd_addr. The module manages the AR (address) and R (data) channels through the AXI4 VALID/READY handshake. o_rvalid reflects m_axi_rvalid, while received data is copied to o_rdata on an accepted transfer (m_axi_rvalid='1' and m_axi_rready='1'). o_rd_done pulses when that transfer is the last one (m_axi_rlast='1').

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_rst

Direction: Input
Width: 1 bit
Description: Synchronous reset

i_read_go

Direction: Input
Width: 1 bit
Description: Rising-edge read trigger

i_rd_addr

Direction: Input
Width: 32 bits
Description: Read address

o_rdata

Direction: Output
Width: 32 bits
Description: Read data

o_rvalid

Direction: Output
Width: 1 bit
Description: Data valid

o_rd_done

Direction: Output
Width: 1 bit
Description: Read done pulse

m_axi_araddr

Direction: Output
Width: 32 bits
Description: AXI Read Address

m_axi_arvalid

Direction: Output
Width: 1 bit
Description: AXI AR Valid

m_axi_arready

Direction: Input
Width: 1 bit
Description: AXI AR Ready

m_axi_rdata

Direction: Input
Width: 32 bits
Description: AXI Read Data

m_axi_rresp

Direction: Input
Width: 2 bits
Description: AXI Read Response

m_axi_rlast

Direction: Input
Width: 1 bit
Description: AXI Read Last

m_axi_rvalid

Direction: Input
Width: 1 bit
Description: AXI R Valid

m_axi_rready

Direction: Output
Width: 1 bit
Description: AXI R Ready

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