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Exercises
16
Done
0
Total
16
TOP_LEVEL - BCD 7-Segment Counter
Wire the provided components into a structural TOP_LEVEL.
N-bit Comparator
Implement a parametric comparator capable of comparing two unsigned values.
Double Flip-Flop Synchronizer
Implement a two-stage synchronizer to safely transfer an asynchronous signal into a clock domain.
Rising Edge Detector
Implement a rising edge detector that generates a one-clock-cycle pulse on each 0→1 transition of the input signal.
Falling Edge Detector
Implement a falling edge detector that generates a one-clock-cycle pulse on each 1→0 transition of the input signal.
4:1 Mux from 2:1 Muxes
Build a 4-to-1 multiplexer by instantiating three 2-to-1 multiplexers from the package.
2-to-4 Decoder
Implement a 2-to-4 binary decoder with active-high one-hot output.
4-to-2 Priority Encoder
Implement a 4-to-2 priority encoder: the binary output gives the index of the highest active bit in `i_d`.
Half Subtractor
Implement a 1-bit half subtractor producing the difference and the outgoing borrow.
8-bit Parity Detector (XOR Tree)
Compute the even parity of an 8-bit word using a 3-level XOR tree.
4-bit Ripple-Carry Adder
Build a 4-bit adder by chaining four 1-bit full-adders provided in the package.
D Flip-flop with Async Set/Reset
Implement a D flip-flop with asynchronous set and reset, both priority over the clock.
T Flip-flop from D Flip-flop
Build a T flip-flop by wiring a D flip-flop with an XOR gate.
3-bit Asynchronous (Ripple) Counter
Build a 3-bit ripple counter by chaining three T flip-flops from the package.
Divide-by-4 Frequency Divider
Cascade two T flip-flops to produce a clock four times slower than `i_clk`.
Serial-to-Parallel Converter
Code a parameterized shift register using a `generate` structure.