BCD Counter

Beginner

00:00

Specification

01General Operation

The BCD counter counts from 0 to 9 on the rising clock edge when enable is active. After 9, it wraps to 0. The o_end output is '1' while the current value is 9.

Reset is asynchronous and active-low.

o_end is a combinational signal

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-low async reset

i_en

Direction: Input
Width: 1 bit
Description: Count enable

o_cpt

Direction: Output
Width: 4 bits (unsigned)
Description: Current count value

o_end

Direction: Output
Width: 1 bit
Description: End of count flag (=1 when counter is 9)

← SPI Master Mode 0

Chargement…