SPI Master Mode 0

The module implements an SPI master in mode 0 (CPOL=0, CPHA=0) with a configurable clock divider. A transaction starts on command and transfers data serially, MSB first. The module manages Chip Select and signals availability.

Reset is synchronous and active-high.

Generics:

• g_clk_div : integer (default 4) - Number of system clock cycles per SCK half-period. With g_clk_div=4, SCK toggles every 4 cycles → SCK frequency = Fclk/8.

• State machine for protocol management
• SCK frequency is set by the g_clk_div generic