8-bit SPI Master

Beginner

00:00

Specification

01General Operation

The SPI master generates the SCK clock by dividing the system clock (configurable via generic). A transaction starts on command and sends/receives a configurable number of bits in mode 0 (CPOL=0, CPHA=0). The module manages Slave Select and signals when busy.

Reset is synchronous and active-high.

SCK frequency is set by the g_CLK_DIV generic
Data is transmitted MSB first

02Interface

Generics:

g_CLK_DIV : positive (default 4) - System cycles per SCK half-period
g_DATA_WIDTH : positive (default 8) - Bits per frame

Ports:

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_rst

Direction: Input
Width: 1 bit
Description: Synchronous reset

i_start

Direction: Input
Width: 1 bit
Description: Start transaction

i_data

Direction: Input
Width: g_DATA_WIDTH
Description: Data to transmit

o_sck

Direction: Output
Width: 1 bit
Description: Generated SPI clock

o_ss_n

Direction: Output
Width: 1 bit
Description: Active-low Slave Select

o_mosi

Direction: Output
Width: 1 bit
Description: Master Out Slave In

i_miso

Direction: Input
Width: 1 bit
Description: Master In Slave Out

o_data

Direction: Output
Width: g_DATA_WIDTH
Description: Received data

o_data_valid

Direction: Output
Width: 1 bit
Description: Data valid pulse

o_busy

Direction: Output
Width: 1 bit
Description: Transaction in progress

← SPI Slave (CPOL=0, CPHA=1)

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