SPI Slave (CPOL=0, CPHA=1)

The module implements an SPI slave in mode 1 (CPOL=0, CPHA=1). Data is sampled on the falling edge of i_sclk. While i_ss_n is active low, the slave receives 32 serial bits on i_MOSI. The received frame and its completion indicator are then transferred into the i_clk domain through two synchronization stages.

i_reset_n is active low: it asynchronously resets SPI capture and is sampled on the rising edge of i_clk for the synchronization registers.

• The SPI bit counter and shift register are also reset asynchronously while i_ss_n is inactive high
• o_top is the completion indicator synchronized into the i_clk domain