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4-Bit Ring Counter

Beginner

Simulate (GHDL)

00:00

Specification

01General Operation

4-bit ring counter: a single '1' walks through the register by left-rotation.

Behaviour:

Reset (i_reset='1'): o_q ← "0001".
Rising edge of i_clk: left rotation, the leaving MSB re-enters through the LSB.

Generated sequence:

0001 → 0010 → 0100 → 1000 → 0001 → ...

*Asynchronous active-high reset.*

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-high async reset

o_q

Direction: Output
Width: 4 bits
Description: Counter output

← 4-Bit Down Counter