Single-Port RAM 256x8

Synchronous single-port RAM of 256 words × 8 bits. Read and write share the same i_addr and data port.

Behaviour:

• Write (i_we='1'): on the rising edge of i_clk, i_data is latched at address i_addr.
• Read (i_we='0'): on the rising edge, o_data receives the contents of i_addr. 1-cycle latency.
• During a write, o_data reflects the newly-written value (*write-first* mode).

*Memory is inferred as a BRAM block by synthesis tools.*