Single-Port RAM 256x8

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01General Operation

Synchronous single-port RAM of 256 words × 8 bits. Read and write share the same i_addr and data port.

Behaviour:

Write (i_we='1'): on the rising edge of i_clk, i_data is latched at address i_addr.
Read (i_we='0'): on the rising edge, o_data receives the contents of i_addr. 1-cycle latency.
During a write, o_data reflects the newly-written value (*write-first* mode).

*Memory is inferred as a BRAM block by synthesis tools.*

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_we`	Input	1 bit	Write enable
`i_addr`	Input	8 bits	Address (0 to 255)
`i_data`	Input	8 bits	Data to write
`o_data`	Output	8 bits	Data read

Chargement…