Dual-Port RAM 128x16

Synchronous dual-port RAM of 128 words × 16 bits. Port A handles writes, port B handles reads, with two independent addresses.

Behaviour:

• Port A (write): on the rising edge of i_clk, if i_we_a='1', i_data_a is written at i_addr_a.
• Port B (read): on the rising edge of i_clk, o_data_b receives the contents of i_addr_b. 1-cycle latency.
• Both ports run concurrently on the same clock.

*Inferred as a *Simple Dual-Port* BRAM. Collision behaviour (read/write to the same address) is target-technology defined.*