Dual-Port RAM 128x16

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01General Operation

Synchronous dual-port RAM of 128 words × 16 bits. Port A handles writes, port B handles reads, with two independent addresses.

Behaviour:

Port A (write): on the rising edge of i_clk, if i_we_a='1', i_data_a is written at i_addr_a.
Port B (read): on the rising edge of i_clk, o_data_b receives the contents of i_addr_b. 1-cycle latency.
Both ports run concurrently on the same clock.

*Inferred as a *Simple Dual-Port* BRAM. Collision behaviour (read/write to the same address) is target-technology defined.*

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_we_a`	Input	1 bit	Write enable port A
`i_addr_a`	Input	7 bits	Address port A (0 to 127)
`i_data_a`	Input	16 bits	Data to write port A
`i_addr_b`	Input	7 bits	Address port B (0 to 127)
`o_data_b`	Output	16 bits	Data read port B

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