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The module divides the input clock frequency by 2 × G_HALF. The output o_clk toggles every G_HALF clock periods, producing a divided frequency.
Reset is asynchronous and active-high.
G_HALF (default 50,000,000)i_clki_reseto_clkGeneric:
| Name | Type | Description |
|---|---|---|
G_HALF | integer | Half-period in clock cycles (total division = 2 × G_HALF) |