Vivado and Other FPGA Tools

Overview of FPGA development tools - proprietary and open-source: Vivado, Quartus Prime, Libero SoC, and open alternatives.

Vivado and Other FPGA Tools

Writing VHDL is one thing. Turning it into a physical circuit is another: you need a synthesis and implementation tool matched to the target FPGA family. Each vendor mandates its own tool, and their differences are significant.

Overview

Vivado (AMD / Xilinx)

Vivado is the reference tool for this course because Xilinx FPGAs (7-Series, Zynq) are ubiquitous in industry and education.

Strengths

• Block Design: graphical IP assembly (ZYNQ PS, AXI Interconnect, DMA…) via drag and drop
• Timing Analysis (STA) with detailed WNS/WHS reports
• Large IP Catalog (FFT, FIR, Ethernet, PCIe, DDR…)
• Simulation: built-in Vivado Simulator (XSIM), VHDL-2008 compatible
• ILA (Integrated Logic Analyzer): in-situ debug without external equipment
• Tcl: the entire GUI is scriptable

Licenses

Vivado ML Edition - Standard   → free, limited to small FPGAs (Artix-7, Spartan-7)
Vivado ML Edition - Enterprise → paid, all devices, advanced features (partial reconfiguration…)

The free edition is sufficient for the vast majority of projects in this course (Nexys A7, Basys 3, PYNQ-Z2).

Typical Workflow

VHDL code → Synthesis → Implementation → Bitstream → FPGA Programming
                ↓               ↓
           Elaboration     Place & Route
           (RTL → netlist)  (timing closure)

Quartus Prime (Intel / Altera)

Intel's equivalent of Vivado. Widely used in telecom and defense.

Strengths

• Platform Designer (formerly Qsys): equivalent of Block Design for Altera IPs (Avalon bus)
• TimeQuest: STA engine renowned for its accuracy
• SignalTap II: in-situ logic analyzer (Xilinx ILA equivalent)
• Tcl scripting interface as well

Licenses

Quartus Prime Lite     → free, Cyclone IV/V/10, MAX 10
Quartus Prime Standard → paid
Quartus Prime Pro      → paid, Agilex, Stratix 10

Key Differences from Vivado

The SDC constraint format is shared by Quartus, Libero, and open-source tools - it is the actual industry standard. Vivado uses XDC, which is an extension of SDC.

Libero SoC (Microchip / Microsemi)

Dedicated to Microsemi FPGAs, rarely seen in education but heavily used in aerospace, space, and defense (radiation tolerance, reliability).

Strengths

• SmartDesign: graphical assembly similar to Block Design
• Robust STA, DO-254 certified (avionics)
• Support for Flash FPGA technology (non-volatile, instant startup)

License

Free for small devices (IGLOO2, SmartFusion2 up to a certain size).

Open-Source Tools

A fully free toolchain exists, primarily targeting Lattice FPGAs (iCE40, ECP5):

VHDL → GHDL (synthesis) → Yosys (netlist) → nextpnr (place & route) → Bitstream

Advantages / Limitations

Advantages:

• Completely free, reproducible, CI/CD scriptable
• Ideal for maker projects (iCEBreaker, OrangeCrab…)

Limitations:

• Partial VHDL-2008 support in GHDL (Yosys bridge still maturing)
• No support for large Xilinx/Intel FPGAs
• No IP catalog, no Block Design

What Changes Between Tools

Timing Constraints

Constraint file syntax differs:

# Vivado (.xdc)
create_clock -period 10.000 -name sys_clk [get_ports i_clk]
set_input_delay -clock sys_clk 2.0 [get_ports i_data]

# Quartus / Libero / nextpnr (.sdc)
create_clock -period 10.000 [get_ports i_clk]
set_input_delay -clock { i_clk } 2.0 [get_ports i_data]

Vendor-Specific Attributes

Some VHDL attributes are tool-specific and ignored (or rejected) by others:

-- Xilinx/Vivado only
attribute ASYNC_REG : string;
attribute ASYNC_REG of r_sync1 : signal is "TRUE";
 
attribute KEEP : string;
attribute KEEP of r_sig : signal is "TRUE";  -- prevents optimization
 
-- Intel/Quartus only
attribute preserve : boolean;
attribute preserve of r_sig : signal is true;

These attributes are ignored during GHDL simulation - they only have meaning for the target synthesizer.

Directly Instantiated Primitives

Each vendor exposes low-level non-portable primitives:

-- Xilinx: BUFG, IBUF, OBUF, RAMB36E2, DSP48E2...
BUFG_inst : BUFG port map (O => clk_buf, I => clk_in);
 
-- Intel: ALTPLL, altera_std_synchronizer, ALTDPRAM...
-- Microchip: GL (global buffer), MSS (hard ARM core)...

Once code instantiates primitives, it is no longer portable across vendors.

Which Tool to Choose?

You have a Xilinx/AMD FPGA?          → Vivado (this course)
You have an Intel/Altera FPGA?       → Quartus Prime
You have a Microchip/Microsemi FPGA? → Libero SoC
You have an iCE40 or ECP5?           → nextpnr + Yosys (or iCEcube2)
You just want to simulate VHDL?      → GHDL + GTKWave (free, universal)

The structural and behavioral VHDL you write in this course is portable across all these tools. Timing constraints, vendor-specific attributes, and directly instantiated primitives are what create vendor lock-in.

📝 Test your knowledge - Chapter quiz