Overview of FPGA development tools - proprietary and open-source: Vivado, Quartus Prime, Libero SoC, and open alternatives.
Vivado and Other FPGA Tools
Writing VHDL is one thing. Turning it into a physical circuit is another: you need a synthesis and implementation tool matched to the target FPGA family. Each vendor mandates its own tool, and their differences are significant.
Overview
Tool
Vendor
FPGA Family
Vivado
AMD (ex-Xilinx)
7-Series, UltraScale, UltraScale+, Zynq, Versal
ISE
AMD (ex-Xilinx)
Spartan-3/6, Virtex-4/5/6 (end of life)
Quartus Prime
Intel (ex-Altera)
Cyclone, Arria, Stratix, Agilex
Libero SoC
Microchip (ex-Microsemi)
PolarFire, IGLOO2, SmartFusion2
iCEcube2 / Diamond
Lattice
iCE40, ECP5, MachXO
Radiant
Lattice
Certus, CrossLink-NX
Vivado (AMD / Xilinx)
Vivado is the reference tool for this course because Xilinx FPGAs (7-Series, Zynq) are ubiquitous in industry and education.
Strengths
Block Design: graphical IP assembly (ZYNQ PS, AXI Interconnect, DMA…) via drag and drop
Timing Analysis (STA) with detailed WNS/WHS reports
Intel's equivalent of Vivado. Widely used in telecom and defense.
Strengths
Platform Designer (formerly Qsys): equivalent of Block Design for Altera IPs (Avalon bus)
TimeQuest: STA engine renowned for its accuracy
SignalTap II: in-situ logic analyzer (Xilinx ILA equivalent)
Tcl scripting interface as well
Licenses
Quartus Prime Lite → free, Cyclone IV/V/10, MAX 10Quartus Prime Standard → paidQuartus Prime Pro → paid, Agilex, Stratix 10
Key Differences from Vivado
Aspect
Vivado
Quartus
IP bus
AXI4
Avalon
Built-in simulator
XSIM
ModelSim-Intel (limited free)
Constraint syntax
XDC (Tcl-based)
SDC (Synopsys Design Constraints)
Timing reports
WNS / WHS / TNS
Slack, Fmax
The SDC constraint format is shared by Quartus, Libero, and open-source tools - it is the actual industry standard. Vivado uses XDC, which is an extension of SDC.
Libero SoC (Microchip / Microsemi)
Dedicated to Microsemi FPGAs, rarely seen in education but heavily used in aerospace, space, and defense (radiation tolerance, reliability).
Strengths
SmartDesign: graphical assembly similar to Block Design
Robust STA, DO-254 certified (avionics)
Support for Flash FPGA technology (non-volatile, instant startup)
License
Free for small devices (IGLOO2, SmartFusion2 up to a certain size).
Some VHDL attributes are tool-specific and ignored (or rejected) by others:
-- Xilinx/Vivado onlyattribute ASYNC_REG : string;attribute ASYNC_REG of r_sync1 : signal is "TRUE";attribute KEEP : string;attribute KEEP of r_sig : signal is "TRUE"; -- prevents optimization-- Intel/Quartus onlyattribute preserve : boolean;attribute preserve of r_sig : signal is true;
These attributes are ignored during GHDL simulation - they only have meaning for the target synthesizer.
Directly Instantiated Primitives
Each vendor exposes low-level non-portable primitives:
-- Xilinx: BUFG, IBUF, OBUF, RAMB36E2, DSP48E2...BUFG_inst : BUFG port map (O => clk_buf, I => clk_in);-- Intel: ALTPLL, altera_std_synchronizer, ALTDPRAM...-- Microchip: GL (global buffer), MSS (hard ARM core)...
Once code instantiates primitives, it is no longer portable across vendors.
Which Tool to Choose?
You have a Xilinx/AMD FPGA? → Vivado (this course)You have an Intel/Altera FPGA? → Quartus PrimeYou have a Microchip/Microsemi FPGA? → Libero SoCYou have an iCE40 or ECP5? → nextpnr + Yosys (or iCEcube2)You just want to simulate VHDL? → GHDL + GTKWave (free, universal)
The structural and behavioral VHDL you write in this course is portable across all these tools. Timing constraints, vendor-specific attributes, and directly instantiated primitives are what create vendor lock-in.