Advanced VHDL Concepts

Distinguish elaboration, simulation and synthesis, then cover CDC, latency and advanced genericity.

Why This Chapter

At this point, the goal is not to stack more syntax. The important point is understanding when a construct acts:

The next chapters detail IEEE functions, generate, fixed_pkg, packages and attributes. Here, we keep an overview to avoid confusion.

Phase	Role	Example
Elaboration	Build hierarchy before simulation/synthesis	`generic`, `generate`
Simulation	Execute the model in the simulator	`wait for`, `assert`, files
Synthesis	Turn RTL into registers, LUTs, DSPs, BRAMs	`process`, signals, operators

A for ... generate does not loop at runtime. It creates hardware blocks during elaboration.

g_regs :

Construct	Recommended use
`wait for 10 ns`	Testbench
`file`, `textio`, `hread`	Testbench
`real` as a signal	Simulation, not RTL
Simple `assert`	Possible in RTL, mostly verification/simulation
`rising_edge(i_clk)`	Synchronous RTL
`process(i_clk)`	Synchronous RTL

Topic	Question to ask
`generate`	Is this a repeated hardware structure?
Testbench	Is this a simulation scenario?
CDC	Does the signal cross a clock domain?
Pipeline	What is the exact latency?
Genericity	Is this truly reusable?