VHDL Signals vs Variables vs Constants: Key Differences
Compare VHDL signals, variables, and constants, including declaration scope, update timing, synthesis behavior, and when to use each one.
The Three Storage Types
| Signal | Variable | Constant | |
|---|---|---|---|
| Declaration | Architecture area or port | Inside a process or subprogram | Architecture, package |
| Update | After delta-cycle (deferred) | Immediate | Never (read-only) |
| Scope | Entire architecture | Process only | Architecture or global |
| Synthesis | Wire or register | Temporary variable | Synthesis constant |
Signals
Signals are the wires of the circuit. They communicate between concurrent blocks.
architecture rtl of example is
-- Declaration in the architecture area
signal w_intermediate : std_logic;
signal r_counter : unsigned(7 downto 0) := (others => '0');
begin
-- Signal assignments are deferred
w_intermediate <= i_a AND i_b;
o_result <= w_intermediate OR i_c;
end architecture