Packages and Subprograms

Organize VHDL with reusable packages, functions and procedures.

Why Use a Package

A package groups what must be shared between several VHDL files:

custom types;
common constants;
subtypes;
function and procedure declarations;
component declarations, when the project uses them.

Without a package, the same definitions are copied into several architectures. That often creates inconsistencies.

Package Declaration

The package declaration exposes the interface: what other files can use.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
package video_pkg is
 
  subtype t_color is unsigned(7 downto 0);
 
  type t_rgb is record
    red   : t_color;
    green : t_color;
    blue  : t_color;
    valid : std_logic;
  end record t_rgb;
 
  constant

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
library work;
use work.video_pkg.ALL;
 
entity pixel_gate is
  port (
    i_pixel : in  t_rgb;
    o_red   : out std_logic_vector(7 downto 0)
  );
end entity pixel_gate;
 
architecture rtl of pixel_gate is
begin
  o_red <= std_logic_vector(i_pixel.red) when is_valid_pixel(i_pixel) else x"00";
end architecture rtl;

function parity_even(i_data : std_logic_vector) return std_logic is
  variable v_parity : std_logic := '0';
begin
  for i in i_data'range loop
    v_parity := v_parity xor i_data(i);
  end loop;
 
  return v_parity;
end function parity_even;

procedure drive_byte(
  signal   o_bus   : out std_logic_vector(7 downto 0);
  constant i_value : in  natural
) is
begin
  o_bus <= std_logic_vector(to_unsigned(i_value, o_bus'length));
end procedure drive_byte;

Need	Choice
Compute one value	Function
Factor a testbench check	Procedure
Modify several outputs	Procedure
Share types and constants	Package

Packages and Subprograms

Why Use a Package

Package Declaration

Package Body

Use a Package

Function

Procedure

Function or Procedure

Best Practices

Key Point