VHDL Attributes: 'range, 'length, 'high, and 'low

Learn how VHDL attributes make reusable, width-independent code and when to use 'range, 'length, 'high, 'low, and synthesis attributes.

Why Attributes Matter

An attribute asks a type, signal or range for information. The most useful ones avoid hardcoded sizes.

signal r_data : std_logic_vector(15 downto 0);
 
constant c_WIDTH : natural := r_data'length;

If r_data changes from 16 to 32 bits, c_WIDTH follows automatically.

Range Attributes