Fixed-point with fixed_pkg

Understand ufixed, sfixed, fractional bits, resize and conversion to std_logic_vector.

Why fixed-point

An FPGA naturally manipulates bits. To represent values such as 0.75, -1.25 or a filter gain, floating-point is often avoided. A common solution is fixed-point: a binary integer with a known binary point position.

Example on 8 bits in Q4.4:

4 bits for the integer part;
4 bits for the fractional part;
the physical value is the binary word divided by 2^4.

The `fixed_pkg` package

VHDL-2008 provides fixed_pkg:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.FIXED_PKG.ALL;

It mainly defines:

Type	Use
`ufixed`	unsigned fixed-point number

entity fixed_adapter is
  port (
    i_x : in  std_logic_vector(11 downto 0);
    o_y : out std_logic_vector(11 downto 0)
  );
end entity fixed_adapter;
 
architecture rtl of fixed_adapter is
  signal w_x : sfixed(0 downto -11);
  signal w_y : sfixed(0 downto -11);
begin
  w_x <= to_sfixed(i_x, w_x'high, w_x'low);
  w_y <= resize(w_x, w_y'high, w_y'low);
 
  o_y <= to_slv(w_y);
end architecture rtl;

Need	Choice
Positive fractional value	`ufixed`
Signed fractional value	`sfixed`
Adapt a format	`resize`
Convert from a port	`to_sfixed` or `to_ufixed`
Convert to a port	`to_slv`
Real-valued testbench calculations	`real`, not synthesizable RTL

Fixed-point with fixed_pkg

Why fixed-point

The `fixed_pkg` package

Simple example

Signed: `sfixed`

Conversion from and to ports

Constants and testbench

Saturation and rounding

Best practices

Key takeaways

Fixed-point with fixed_pkg

Why fixed-point

The fixed_pkg package

Simple example

Signed: sfixed

Conversion from and to ports

Constants and testbench

Saturation and rounding

Best practices

Key takeaways

The `fixed_pkg` package

Signed: `sfixed`