Generics and generate

Parameterize a VHDL block with generics and generate repeated or optional structures.

General idea

A generic parameterizes a VHDL block before synthesis. A generate statement creates repeated or conditional structure during design elaboration.

The important difference:

an if inside a process describes a choice that exists in hardware;
an if ... generate decides whether a block exists in hardware at all.

Width generic

The most common case is bus width.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity counter is
  generic (
    g_WIDTH : positive := 8
  );
  port (
    i_clk : in  std_logic;

entity reg_bank is
  generic (
    g_WIDTH : positive := 8
  );
  port (
    i_clk : in  std_logic;
    i_d   : in  std_logic_vector(g_WIDTH - 1 downto 0);
    o_q   : out std_logic_vector(g_WIDTH - 1 downto 0)
  );
end entity reg_bank;
 
architecture rtl of reg_bank is
begin
  g_bits : for i in 0 to g_WIDTH - 1 generate
    p_bit : process(i_clk)
    begin
      if rising_edge(i_clk) then
        o_q(i) <= i_d(i);
      end if;
    end process p_bit;
  end generate g_bits;
end architecture rtl;

entity pipeline_stage is
  generic (
    g_REGISTER_OUTPUT : boolean := true
  );
  port (
    i_clk : in  std_logic;
    i_a   : in  unsigned(7 downto 0);
    i_b   : in  unsigned(7 downto 0);
    o_y   : out unsigned(8 downto 0)
  );
end entity pipeline_stage;
 
architecture rtl of pipeline_stage is
  signal w_sum : unsigned(8 downto 0);
  signal r_y   : unsigned(8 downto 0);
begin
  w_sum <= resize(i_a, w_sum'length) + resize(i_b, w_sum'length);
 
  g_registered : if g_REGISTER_OUTPUT generate
    p_reg : process(i_clk)
    begin
      if rising_edge(i_clk) then
        r_y <= w_sum;
      end if;
    end process p_reg;
 
    o_y <= r_y;
  end generate g_registered;
 
  g_comb : if not g_REGISTER_OUTPUT generate
    o_y <= w_sum;
  end generate g_comb;
end architecture rtl;

Need	Tool
Parameterized width	`generic g_WIDTH`
Parameterized depth	`generic g_DEPTH`
Repeat N instances	`for ... generate`
Enable or remove a block	`if ... generate`
Change at runtime	signal or register, not `generic`

Generics and generate

General idea

Width generic

Instantiation with `generic map`

`for ... generate`

`if ... generate`

Best practices

VHDL-2008: more advanced generics

Key takeaways

Generics and generate

General idea

Width generic

Instantiation with generic map

for ... generate

if ... generate

Best practices

VHDL-2008: more advanced generics

Key takeaways

Instantiation with `generic map`

`for ... generate`

`if ... generate`