VHDL File Architecture

The two fundamental blocks: the entity and the architecture.

Structure of a VHDL File

Each VHDL file generally contains two mandatory blocks:

The entity: defines the external interface (input/output ports)
The architecture: describes the internal behavior

-- 1. Library declarations
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
-- 2. Entity
entity entity_name is
  generic (
    -- generic parameters (optional)
  );
  port (
    -- input/output ports
  );
end entity entity_name;
 
-- 3. Architecture
architecture rtl of entity_name is
  -- declaration area (signals, constants, components)
begin
  -- description area (concurrent logic and processes)
end architecture rtl;

Libraries

Before describing a circuit, declare the necessary libraries.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;   -- std_logic, std_logic_vector types
use IEEE.NUMERIC_STD.ALL;      -- unsigned, signed, conversions

Library	Main Content
`IEEE.STD_LOGIC_1164`	Types `std_logic`, `std_logic_vector`
`IEEE.NUMERIC_STD`	Types `unsigned`, `signed`, arithmetic operations
`STD.STANDARD`	Auto-loaded - types `bit`, `integer`, `boolean`

Warning: Do not use IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED - these non-standard libraries cause conflicts. Prefer IEEE.NUMERIC_STD.

The Entity

The entity represents the external view of the component: its schematic symbol.

entity adder is
  generic (
    g_WIDTH : integer := 8   -- configurable parameter
  );
  port (
    i_clk   : in  std_logic;
    i_rst   : in  std_logic;
    i_a     : in  std_logic_vector(g_WIDTH-1 downto 0);
    i_b     : in  std_logic_vector(g_WIDTH-1 downto 0);
    o_sum   : out std_logic_vector(g_WIDTH downto 0)
  );
end entity adder;

Port Modes

Mode	Direction	Usage
`in`	Input only	Control signals, input data
`out`	Output only	Results, outputs
`inout`	Bidirectional	Tristate bus (rare in modern FPGA)
`buffer`	Output readable internally	Avoid: prefer an internal signal

The Architecture

The architecture defines how the circuit works internally.

architecture rtl of adder is
  -- Declaration area
  signal w_carry : std_logic;
  constant c_ZERO : std_logic_vector(g_WIDTH-1 downto 0) := (others => '0');
 
begin
  -- Description area (all concurrent)
  o_sum <= ('0' & i_a) + ('0' & i_b);
 
end architecture rtl;

Common Architecture Names

Name	Meaning
`rtl`	Register Transfer Level (synthesizable)
`behavioral`	Behavioral (sometimes simulation only)
`structural`	Component instantiation
`tb`	Testbench

Concurrency in the Architecture

In VHDL, everything in the begin ... end area executes in parallel, like electrical wires:

architecture rtl of example is
begin
  -- These three statements are all active simultaneously
  o_y1 <= i_a AND i_b;
  o_y2 <= i_a OR  i_c;
  o_y3 <= NOT i_a;
end architecture rtl;

This is not sequential programming! Think in terms of hardware.

Comments and Style

-- Single-line comment (double dash)
 
-- No /* */ comments in standard VHDL
-- VHDL-2008 adds /* */ comments but few tools support them
 
entity my_component is  -- end-of-line comment OK

Case Conventions

VHDL is case-insensitive: Signal, SIGNAL, signal are identical. By convention:

Keywords in lowercase
Constants and generics in UPPERCASE
Signals and ports with prefixes (see course 07 - Coding Rules)

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