Testbenches and Simulation

Write self-checking VHDL testbenches with a DUT, clock, reset, stimuli, assertions, and verification before synthesis.

What is a Testbench?

A testbench (TB) is a VHDL simulation file that:

Instantiates the Device Under Test (DUT)
Generates stimuli (input signals)
Observes and verifies outputs

A testbench has no ports - it is a closed environment.

entity tb_mux4to1 is
  -- No ports!
end entity tb_mux4to1;

Typical Testbench Structure

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity tb_mux4to1 is
end entity tb_mux4to1;
 
architecture tb of tb_mux4to1 is
 
  -- Simulation constants
  constant c_CLK_PERIOD : time := 10 ns;  -- 100 MHz
 
  -- Signals to connect to the DUT

-- Clock generation process
p_clk : process
begin
  i_clk <= '0';
  wait for c_CLK_PERIOD / 2;
  i_clk <= '1';
  wait for c_CLK_PERIOD / 2;
end process p_clk;
 
-- Concurrent alternative
i_clk <= not i_clk after c_CLK_PERIOD / 2;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity tb_counter is
end entity tb_counter;
 
architecture tb of tb_counter is
 
  constant c_CLK_PERIOD : time := 10 ns;
 
  signal i_clk : std_logic := '0';
  signal i_rst : std_logic := '1';
  signal o_cnt : std_logic_vector(3 downto 0);
 
begin
 
  -- Clock generation
  i_clk <= not i_clk after c_CLK_PERIOD / 2;
 
  -- DUT
  DUT : entity work.counter_4bit
    port map (
      i_clk => i_clk,
      i_rst => i_rst,
      o_cnt => o_cnt
    );
 
  -- Stimuli
  p_test : process
  begin
    -- Reset active for 3 cycles
    i_rst <= '1';
    wait for 3 * c_CLK_PERIOD;
    assert unsigned(o_cnt) = 0 report "Reset failed" severity error;
 
    -- Start counting
    i_rst <= '0';
    wait for 5 * c_CLK_PERIOD;
    assert unsigned(o_cnt) = 5 report "Counting incorrect" severity error;
 
    -- Wait for overflow (16 total cycles = back to 0)
    wait for 11 * c_CLK_PERIOD;
    assert unsigned(o_cnt) = 0 report "Overflow incorrect" severity error;
 
    report "Testbench completed successfully" severity note;
    wait;
  end process p_test;
 
end architecture tb;

Instruction	Usage
`wait for 10 ns;`	Wait a fixed duration
`wait until rising_edge(i_clk);`	Wait for a clock edge
`wait until i_valid = '1';`	Wait for a condition
`wait;`	Stop simulation
`assert condition report "msg" severity level;`	Verification

-- Before the begin of the tb architecture
procedure check_slv(
  constant i_name     : in string;
  constant i_observed : in std_logic_vector;
  constant i_expected : in std_logic_vector
) is
begin
  assert i_observed = i_expected
    report i_name
      & " expected=0x" & to_hstring(i_expected)
      & " observed=0x" & to_hstring(i_observed)
    severity error;
end procedure check_slv;

Level	Effect
`note`	Informational message
`warning`	Warning, simulation continues
`error`	Error, simulation may continue
`failure`	Immediate simulation stop

Testbenches and Simulation

What is a Testbench?

Typical Testbench Structure

Clock Generation

Complete Testbench for Sequential Circuit

Useful Simulation Instructions

Severity Levels

Factor Verification

End Simulation with `std.env`

Best Practices

Testbenches and Simulation

What is a Testbench?

Typical Testbench Structure

Clock Generation

Complete Testbench for Sequential Circuit

Useful Simulation Instructions

Severity Levels

Factor Verification

End Simulation with std.env

Best Practices

End Simulation with `std.env`