Verification with AXI VIP

Verify an AXI-Lite slave in simulation using a master agent, controlled transactions and protocol checks.

Verify before hardware

An AXI IP can synthesize and still be wrong. A response may use the wrong channel, VALID may incorrectly depend on READY, or a partial write may ignore WSTRB.

AXI Verification IP, or AXI VIP, is a simulation component. It acts as a master, slave or monitor. It generates transactions and checks protocol rules during simulation.

The testbench replaces the processor with an AXI VIP master. It writes several values to the LED controller and reads the register back.

Building the testbench

The simulation Block Design contains AXI VIP, the Device Under Test, or DUT, a clock and reset. The DUT is simply the hardware block being verified. The testbench imports generated packages and creates an agent from the VIP instance interface.

import axi_vip_pkg::*;
import design_axi_vip_0_0_pkg::*;
 
design_axi_vip_0_0_mst_t agent;
 
initial begin
  agent = new("master vip agent", DUT.design_i.axi_vip_0.inst.