DMA, cache and linker script

Move buffers between DDR, OCM and BRAM, maintain cache coherence and place ELF sections in the correct memory.

Why DMA matters

A CPU copy consumes instructions for every word. A Direct Memory Access controller, or DMA, receives a transfer description and becomes a bus master. It moves a block without making the processor copy each word. The processor can then do other work or wait for a completion interrupt.

To make memory and cache effects measurable, this course provides a DMA benchmark. It measures four paths: DDR to DDR, BRAM to BRAM, DDR to BRAM and BRAM to DDR. It repeats 4096-word blocks, measures TTC cycles and checks every destination word. A timing result without data verification can hide an address or cache error.

Preparing a transfer

for (u32 i = 0; i < word_count; i++) {
    source[i] = 0x10000000U + i;
    destination[i] = 0U;
}
 
Xil_DCacheFlushRange((UINTPTR)source, word_count * sizeof(u32));
start_dma(source, destination, word_count);
wait_for_dma_done();
Xil_DCacheInvalidateRange((UINTPTR)destination, word_count