PS and PL Interface with AXI

Select AXI ports between the Processing System and programmable logic, then manage clocks, resets, interrupts and memory coherency.

Two separate paths

A Zynq architecture often separates the control path from the data path.

AXI is a family of communication protocols used inside the chip. AXI-Lite carries simple register reads and writes. AXI-Stream carries a continuous sequence of data without a memory address for every item.

The control path carries little data. The processor writes parameters, starts an IP and reads its status. AXI-Lite fits this requirement.

The data path carries buffers or a continuous stream. A buffer is a reserved memory area that temporarily holds data. This path uses an AXI master in the PL, a DMA and a port to PS memory.

This split avoids using the processor to copy every word. Software supervises the operation. Hardware moves and processes data.

Read a port name

The M_AXI or S_AXI prefix is written from the viewpoint of the block that owns the port.

An M_AXI_GP0 port on the PS is a master port. The PS starts transactions toward a PL peripheral.

An S_AXI_HP0 port on the PS is a slave port. A master in the PL uses it to reach DDR or another PS resource.

The drawing direction does not define the master. The block that starts a transaction is the master. The block that answers it is the slave. The block that owns the port defines the prefix.

Zynq-7000 ports