APU, RPU and Memory
Understand application and real-time processors, caches, address spaces and memory resources in a Zynq system.
Two processor types
A Zynq UltraScale+ MPSoC has an APU and an RPU. They serve different requirements.
The Application Processing Unit uses Cortex-A53 cores. It targets rich applications, Linux and workloads that benefit from caches, virtual memory and multiple cores.
The Real-time Processing Unit uses two Cortex-R5 cores. It targets deterministic response, which means that execution time remains predictable, and low latency. The cores can run separately or in lockstep. In lockstep mode, both cores execute the same instructions and compare their results to detect faults.
| Property | APU | RPU |
|---|---|---|
| Processor | Cortex-A53 | Cortex-R5 |
| Main use | Applications and operating systems | Real-time and safety functions |
| Memory management | MMU and virtual memory | MPU without address translation |
| Local memory | Caches | TCM and caches |
| Redundant execution | Not the main operating mode | Lockstep mode available |
The APU
The APU is the general-purpose high-performance processing unit in the PS. Each core has an L1 cache. The cores share an L2 cache and coherency infrastructure.
The Memory Management Unit, or MMU, translates virtual addresses into physical addresses and applies memory attributes. Linux uses it for process isolation and memory management. Bare-metal software can also configure attributes to distinguish normal memory from peripheral registers.
Peripheral registers must not behave like cached RAM. Xilinx input and output functions preserve hardware access semantics more clearly.
#include "xil_io.h"
u32 read_status(UINTPTR base)
{
return Xil_In32(base + 0x