AXI-Lite Protocol

AXI-Lite: the simplified AXI variant for configuration registers and control interfaces.

What is AXI-Lite?

AXI-Lite is a simplified version of the AXI protocol developed by ARM as part of the AMBA architecture. It is particularly suited for control and configuration communications within a SoC.

Unlike full AXI4, AXI-Lite:

• Does not support burst (one data beat per transaction)
• Has a fixed data width
• Uses fewer signals

Comparison with AXI

Read

Only 7 signals are needed for a complete read transaction.

Sequence:

1. Master places the address on ARADDR and asserts ARVALID.
2. Slave asserts ARREADY, indicating it accepts the address.
3. Master and Slave may deassert ARVALID and ARREADY after the handshake.
4. Master asserts RREADY when it is ready to receive data.
5. Slave sends data on RDATA and asserts RVALID (RRESP may indicate an error).
6. On the rising clock edge where RREADY and RVALID are both asserted, data transfers. Slave then deasserts RVALID if it has no more data.

Write

Write transactions require 10 signals.

Sequence:

1. Master places the address on AWADDR.
2. Master asserts AWVALID and waits for AWREADY from the Slave.
3. Master places data on WDATA (and byte mask on WSTRB).
4. Master asserts WVALID and waits for WREADY from the Slave.
5. Master waits for BVALID from the Slave.
6. Slave provides the response on BRESP (OKAY if successful).
7. Master asserts BREADY to acknowledge the response.

Signal Summary

AXI-Lite is the protocol of choice for configuration registers and simple peripherals in a Zynq SoC.

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