I2C Protocol

I2C addressing, ACK/NACK, START/STOP conditions and VHDL FSM structure.

What is I2C?

The I2C (Inter-Integrated Circuit) protocol was developed by Philips Semiconductors (now NXP) in 1982. It enables communication between multiple devices using only two wires.

Key characteristics:

2 wires: SDA (data) and SCL (clock)
Open-drain: lines require external pull-up resistors
Multi-master: hardware arbitration between multiple masters
Addressing: each slave has a unique address (7 or 10 bits)
ACK/NACK: acknowledgment after each byte

I2C Signals

Signal	Type	Description
SDA	Bidirectional open-drain	Serial Data
SCL	Bidirectional open-drain	Serial Clock

Both lines are pulled high by pull-up resistors. Any device on the bus can pull a line low (open-drain), but none can force it high - only the pull-up resistors do that.

Start and Stop Conditions

I2C uses two special conditions that violate normal data transitions (data stable while SCL high):

I2C timing diagram

START condition: SDA falls while SCL is high. STOP condition: SDA rises while SCL is high.

SDA data must only change while SCL is low - except for START and STOP conditions.

I2C Frame

A typical I2C write transaction:

START | Address (7 bits) | R/W='0' | ACK | Data byte | ACK |

library ieee;
use ieee.std_logic_1164.all;
 
entity i2c_master is
  generic (
    g_SYS_CLK_HZ : positive := 100_000_000;  -- 100 MHz
    g_I2C_CLK_HZ : positive := 400_000       -- 400 kHz (Fast mode)
  );
  port (
    i_clk     : in    std_logic;
    i_rst     : in    std_logic;
    i_start   : in    std_logic;
    i_rw      : in    std_logic;  -- '0'=write, '1'=read
    i_addr    : in    std_logic_vector(6 downto 0);
    i_data    : in    std_logic_vector(7 downto 0);
    o_data    : out   std_logic_vector(7 downto 0);
    o_busy    : out   std_logic;
    o_ack_err : out   std_logic;
    io_sda    : inout std_logic;
    io_scl    : inout std_logic
  );
end entity i2c_master;

Advantages	Disadvantages
Only 2 wires	Slower than SPI
Native multi-master	Open-drain requires pull-up resistors
Addressing - no SS_N	More complex protocol
ACK/NACK for verification	Bus capacitance limit (400 pF)

Mode	Max Speed
Standard Mode	100 kbps
Fast Mode	400 kbps
Fast Mode Plus	1 Mbps
High Speed Mode	3.4 Mbps

I2C Protocol

What is I2C?

I2C Signals

Start and Stop Conditions

I2C Frame

ACK and NACK

VHDL Implementation - I2C Master State Machine

Clock Stretching

Multi-Master Arbitration

Standardized Speeds

Advantages and Disadvantages