Avalon Protocol

Avalon-MM/Avalon-ST signals, handshakes and Platform Designer integration.

What is Avalon?

Avalon is a family of interface protocols developed by Intel (formerly Altera) for their Cyclone, Arria, and Stratix FPGAs. It is used in Platform Designer (formerly Qsys) to connect IPs within an FPGA SoC.

The Avalon family includes several variants:

Avalon-MM (Memory Mapped): register and memory access
Avalon-ST (Streaming): continuous data stream
Avalon-Interrupt: interrupt signals
Avalon-Clock: clock distribution
Avalon-Conduit: custom out-of-band signals

Avalon-MM (Memory Mapped)

Main Signals

Signal	Direction (Master)	Description
address	Output	Word address
read	Output	Read request
write	Output	Write request
readdata	Input	Read data (slave → master)
writedata	Output	Write data (master → slave)
byteenable	Output	Active byte mask
waitrequest	Input	Slave requests a wait cycle
readdatavalid	Input	(pipeline) Read data is valid

Avalon-MM Read and Write Cycles

Avalon-MM timing diagrams

The master must hold read and address stable while waitrequest is high.

VHDL Implementation

A zero-latency Avalon-MM slave is the simplest implementation: waitrequest is always low, and reads/writes execute in a single cycle. The slave decodes the address to access an internal register array.

Avalon concepts are practiced through the protocol quizzes and exercises, including Avalon-MM slave implementation work.

Avalon-ST (Streaming)

Signal	Direction (Source)	Description
data	Output	Stream data
valid	Output	Data is valid
ready	Input	Sink can accept data
startofpacket	Output	First beat of a packet
endofpacket	Output	Last beat of a packet
empty	Output	Number of empty bytes in the last beat
error	Output	Error associated with the beat

CLK   : ___‾___‾___‾___‾___‾___‾
valid :    |‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
ready :    |‾‾‾‾‾|_____|‾‾‾‾‾‾‾|
data  :    | D0  |  X  | D1 | D2|
            ↑           ↑    ↑
         transfer  pause  transfers

Criterion	Avalon-MM	AXI-Lite
Standard	Intel/Altera	ARM (AMBA)
Separate channels	No	Yes (5 channels)
Wait mechanism	waitrequest	valid/ready handshake
Native burst	Yes	No (AXI4 full)
Auto-generation	Platform Designer	Vivado IP Integrator
Typical use	Cyclone, Arria, Stratix	Zynq, UltraScale

# Declaring the Avalon-MM interface in the IP TCL file
add_interface s0 avalon slave
set_interface_property s0 addressUnits WORDS
add_interface_port s0 address address 2 Input
add_interface_port s0 read read 1 Input
add_interface_port s0 write write 1 Input
add_interface_port s0 readdata readdata 32 Output
add_interface_port s0 writedata writedata 32 Input
add_interface_port s0 waitrequest waitrequest 1 Output

Avalon Protocol

What is Avalon?

Avalon-MM (Memory Mapped)

Main Signals

Avalon-MM Read and Write Cycles

VHDL Implementation

Avalon-ST (Streaming)

Main Signals

valid/ready Handshake

Avalon-MM vs AXI-Lite Comparison

Key Points

Example: Custom IP in Platform Designer