Wishbone Bus Protocol: Signals, ACK, Pipelining, and VHDL

Learn the Wishbone bus protocol, its master-slave signals and ACK handshake, pipelined transfers, VHDL implementation, and differences from AXI.

What is Wishbone?

Wishbone is an open-source system bus developed by Silicore Corporation and standardized by the OpenCores Foundation. It is widely used in open-hardware designs (OpenCores, LiteX, OpenRISC) as an internal SoC bus.

Key characteristics:

Open-source: free specification
Simple: few signals, easy to implement
Flexible: supports single, burst, and pipelined transfers
Synchronous: all transactions occur on clock edges

Wishbone Signals

Signals are prefixed _i (input) or _o (output) from the master's perspective.

Signal	Direction (Master)	Description
CLK_I	Input	Shared clock
RST_I	Input	Synchronous active-high reset
ADR_O	Output	Address
DAT_O	Output	Data master → slave
DAT_I	Input	Data slave → master
WE_O	Output	Write Enable: '1' = write
SEL_O	Output	Active byte select
STB_O	Output	Strobe: active transaction on this cycle
CYC_O	Output	Cycle: master holds the bus
ACK_I	Input	Acknowledgment: slave completes the transaction
ERR_I	Input	(optional) Error
RTY_I	Input	(optional) Retry

Read and Write Cycles

Wishbone timing diagrams

Criterion	Wishbone	AXI4
Complexity	Simple	Complex
Separate channels	No	Yes (5 channels)
Native burst	Yes (B4)	Yes
Multi-master	Yes (with crossbar)	Yes (with interconnect)
License	Open source	ARM - free but proprietary
Typical use	Open-hardware SoC	Zynq, commercial SoCs

Wishbone Bus Protocol: Signals, ACK, Pipelining, and VHDL

What is Wishbone?

Wishbone Signals

Read and Write Cycles

VHDL Implementation

Pipeline Mode (Wishbone B4)

Key Points

Comparison with AXI