Describing sequential logic

Create clocked registers, handle reset and enable, and understand nonblocking assignments.

When the circuit keeps state

Sequential logic stores a value from one cycle to the next. A flip-flop usually updates its output on a clock edge.

module data_register (
  input  wire       i_clk,
  input  wire       i_reset,
  input  wire       i_enable,
  input  wire [7:0] i_data,
  output reg  [7:0] o_data
);
 
  always @(posedge i_clk) begin
    if (i_reset)
      o_data <= 8'h00;
    else if (i_enable)
      o_data <= i_data;
  end
 
endmodule

posedge i_clk triggers the block on a rising edge. If is 0, no new assignment is made and the register keeps its value. That behavior is intentional here.