Modules, ports, and hierarchy

Declare an interface, choose between wire and reg, then connect several modules cleanly.

The role of a module

A module is the basic building block of Verilog. It can represent a small function, such as a comparator, or the top level of a complete FPGA.

module channel_guard (
  input  wire i_valid,
  input  wire i_ready,
  output wire o_fault
);
 
  assign o_fault = i_valid & ~i_ready;
 
endmodule

The declaration inside the parentheses gives the name, direction, and type of each port. This ANSI-style form is available in Verilog-2001.

Inputs, outputs, and bidirectional ports

A port can have three directions:

inout is mainly useful at physical pins, for example for a truly tri-stated bus. Inside an FPGA, it is usually better to separate the input, output, and enable paths.