ROM, RAM, and FIFO

Describe memories that tools can recognize and handle FIFO boundaries correctly.

A ROM can be described with a case statement

A small constant table is easy to describe with a combinational block. Every address must produce a value.

module opcode_rom (
  input  wire [2:0] i_address,
  output reg  [7:0] o_data
);
 
  always @* begin
    case (i_address)
      3'd0:    o_data = 8'h13;
      3'd1:    o_data = 8'h27;
      3'd2:    o_data = 8'h42;
      3'd3:    o_data = 8'h81;
      3'd4:    o_data = 8'hA5;
      default: o_data = 8'h00;
    endcase
  end
 
endmodule

Depending on its size and the target FPGA, the tool may implement this table with distributed logic or internal memory.

module synchronous_ram #(
  parameter WIDTH = 8,
  parameter ADDRESS_WIDTH = 6
) (
  input  wire                     i_clk,
  input  wire                     i_write_enable,
  input  wire [ADDRESS_WIDTH-1:0] i_address,
  input  wire [WIDTH-1:0]         i_write_data,
  output reg  [WIDTH-1:0]         o_read_data
);
 
  localparam DEPTH = 1 << ADDRESS_WIDTH;
  reg [WIDTH-1:0] memory [0:DEPTH-1];
 
  always @(posedge i_clk) begin
    if (i_write_enable)
      memory[i_address] <= i_write_data;
 
    o_read_data <= memory[i_address];
  end
 
endmodule

module synchronous_fifo #(
  parameter WIDTH = 8,
  parameter ADDRESS_WIDTH = 3
) (
  input  wire                     i_clk,
  input  wire                     i_reset,
  input  wire                     i_write,
  input  wire [WIDTH-1:0]         i_write_data,
  input  wire                     i_read,
  output reg  [WIDTH-1:0]         o_read_data,
  output reg                      o_read_valid,
  output wire                     o_empty,
  output wire                     o_full,
  output wire [ADDRESS_WIDTH:0]   o_level
);
 
  localparam DEPTH = 1 << ADDRESS_WIDTH;
  localparam [ADDRESS_WIDTH:0] DEPTH_COUNT = DEPTH;
 
  reg [WIDTH-1:0] memory [0:DEPTH-1];
  reg [ADDRESS_WIDTH-1:0] write_pointer;
  reg [ADDRESS_WIDTH-1:0] read_pointer;
  reg [ADDRESS_WIDTH:0] count;
 
  wire write_accepted = i_write && !o_full;
  wire read_accepted  = i_read  && !o_empty;
 
  assign o_empty = (count == 0);
  assign o_full  = (count == DEPTH_COUNT);
  assign o_level = count;
 
  always @(posedge i_clk) begin
    if (i_reset) begin
      write_pointer <= 0;
      read_pointer  <= 0;
      count         <= 0;
      o_read_data   <= 0;
      o_read_valid  <= 1'b0;
    end else begin
      o_read_valid <= 1'b0;
 
      if (write_accepted) begin
        memory[write_pointer] <= i_write_data;
        write_pointer <= write_pointer + 1'b1;
      end
 
      if (read_accepted) begin
        o_read_data  <= memory[read_pointer];
        read_pointer <= read_pointer + 1'b1;
        o_read_valid <= 1'b1;
      end
 
      case ({write_accepted, read_accepted})
        2'b10: count <= count + 1'b1;
        2'b01: count <= count - 1'b1;
        default: count <= count;
      endcase
    end
  end
 
endmodule

ROM, RAM, and FIFO

A ROM can be described with a case statement

Describing synchronous RAM

What a FIFO stores

Interface choices must be stated

An asynchronous FIFO is a different circuit

Key points