Literals, vectors, and operators

Write unambiguous constants, manipulate bits, and avoid width and signedness pitfalls.

Giving constants a width

A Verilog constant can specify its width, base, and value:

8'b1010_0110
8'hA6
8'd166
12'o245

These items do not all have the same width: the first three occupy 8 bits, while the last one occupies 12 bits. Underscores improve readability without changing the value.

The general form is width'basevalue. Common bases are b for binary, o for octal, d for decimal, and h for hexadecimal.

An unsized constant such as 5 follows implicit rules that can widen an expression or change its signed interpretation. In RTL, writing 4'd5 or 8'd5 makes the intent clearer.

Vectors and bit selection

wire [

Family	Examples	Result
arithmetic	`+`, `-`, `*`	calculation on numbers
bitwise	`&`, `\|`, `^`, `~`	independent operation on each bit
logical	`&&`, `\|\|`, `!`	true, false, or unknown condition
comparison	`<`, `>=`, `==`, `!=`	one-bit result
reduction	`&bus`, `\|bus`, `^bus`	reduction of a vector to one bit
shift	`<<`, `>>`	movement of bits
conditional	`condition ? a : b`	choice between two values

module word_tools (
  input  wire [7:0]        i_word,
  input  wire signed [7:0] i_delta,
  output wire [3:0]        o_high_nibble,
  output wire              o_odd_parity,
  output wire signed [8:0] o_delta_ext,
  output wire [15:0]       o_repeated
);
 
  assign o_high_nibble = i_word[7:4];
  assign o_odd_parity  = ^i_word;
  assign o_delta_ext   = {i_delta[7], i_delta};
  assign o_repeated    = {2{i_word}};
 
endmodule

Literals, vectors, and operators

Giving constants a width

Vectors and bit selection

Concatenating and repeating

Four logic states

Operator families

Widths and signed numbers

Complete example

Key points