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Short chapter quizzes with maximum XP on the first try and detailed feedback after the correct answer.
Quizzes
36
Done
0
Questions
255
PISO/SIPO registers, synchronous counters, modulo counters and terminal-count signals.
Parity, syndrome, Hamming and correction limits.
Testbench structure, clock generation, stimuli, assertions.
Moore vs Mealy, state encoding, one- or two-process style.
std_logic_1164, numeric_std, std.env, textio and practical simulation functions.
Width parameters, generic map, for generate and conditional generation.
Packages, package body, functions, procedures and shared types.
'length, 'range, 'high, 'low, 'event and synthesis attributes.
Instance configuration, internal constants, and hardware generation.
Reusable calculations, test tasks, and synthesizable repetition.
State register, transitions, outputs, and FSM verification.
Memory inference, synchronous reads, and FIFO handling.
Stimulus, events, nonblocking assignments, and self-checking tests.
Inferred circuit, pipelining, widths, and timing constraints.
RTL, verification, and the role of SystemVerilog additions.
Logic states, widths, extensions, and conversions.
Combinational logic, flip-flops, latches, and assignments.
Shared declarations, typed states, and dependencies.
Dimensions, named fields, and shared views.
Subroutines, simulation time, and dependencies.
Protocol grouping, roles, and connections.
Current state, transitions, outputs, and datapath.
Parameters, corner cases, types, and generation.
Handshake, accumulation, corner cases, and inferred hardware.
Synthesis, mapping, place, route and bitstream.
Visual IP assembly, VHDL packaging, SoC integration.
Latency, throughput, critical path, registers and temporal verification.
Read the information that makes a connection safe.
Check a digital link before wiring it.
Prepare a controlled electrical startup.
Understand local current and placement.
Check the conditions for repeatable startup.
Synchronous serial bus: MOSI, MISO, SCLK, CS, modes 0-3.
Two-wire open-drain serial bus, 7-bit addressing, ACK, start and stop.
Open-source SoC bus: master/slave, cycles, handshake.
Intel/Altera bus family: Avalon-MM, Avalon-ST.