Chargement…
Chargement…
Short chapter quizzes with maximum XP on the first try and detailed feedback after the correct answer.
Quizzes
37
Done
0
Questions
216
Requirements, scenarios, checks, and completion criteria.
Structure, clock, reset, stimulus, checks, and final verdict.
Dynamic arrays, queues, and associative indexes.
Objects, handles, inheritance, and virtual methods.
Constraints, distributions, failures, and reproducibility.
fork, events, mailboxes, and semaphores.
Driver, monitor, reference, and scoreboard.
Local and synchronous checks, reset, X/Z, and failure actions.
Coverpoints, bins, crosses, and closure.
Complete environment, phases, draining, configuration, virtual interfaces, callbacks, and factory.
Setup, hold, slack, critical path, timing constraints.
Zynq architecture, PS-PL communication over AXI, embedded design.
SAR ADC, R-2R DAC, comparator and digital sequencing.
Reason about edges, references, and returns.
Match lines and preserve pairs.
Plan layers and escape a dense package.
Manage the boundary between board and outside world.
Power up and isolate a fault without improvising.
ARM AMBA memory-mapped bus: 5 channels, bursts, IDs, VALID/READY handshake.
Simplified AXI variant: single-beat transactions, no bursts, ideal for register access.
AXI streaming variant: single channel, no address, for DSP / video.
PS, PL, Zynq families and hardware-software partitioning.
Block Design, addresses, validation and XSA export.
Platform, BSP, xparameters and GPIO drivers.
APU, RPU, OCM, TCM, DDR and cache coherency.
AXI ports, control, DMA, clocks, resets and interrupts.
Platform, domain, BSP and driver levels.
Source, GIC, ISR and latency.
Buffers, cache coherence and ELF sections.
BootROM, FSBL, U-Boot and BOOT.BIN.
ILA, software debugger and cross-trigger.
Registers, packaging and driver.
Kernel, Device Tree, GPIO and DMA.
Agents, transactions and protocol verification.
Platform, BSP, build and execution on the board.