Beginner

VHDL - Introduction

Origins, uses and role of VHDL in the FPGA flow.

VHDL - File architecture

Entity, architecture, libraries and ports of a VHDL module.

VHDL - Combinational and sequential

Telling apart memoryless (combinational) and clocked (sequential) logic.

VHDL - Data types

std_logic, std_logic_vector, integer, unsigned, signed and conversions.

VHDL - Operators

Logical, arithmetic, comparison, concatenation and precedence rules.

VHDL - Signals, variables and constants

Differences between signal, variable and constant: scope, update timing, synthesis.

VHDL - Best practices

Naming conventions, code organization and classic pitfalls.

VHDL - The process block

Sensitivity list, sequential vs combinational, latches, process(all).

VHDL - Multiplexers

Three classic ways to write a MUX and what they imply for synthesis.

VHDL - Tools: Vivado, Quartus, GHDL

Picking synthesis and simulation tools depending on the target.

VHDL - Components and instantiation

Building a hierarchical design: declaration, instantiation, port map.

FPGA

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FPGA

FPGA - Internal architecture

LUTs, flip-flops, BRAMs, DSPs, interconnects and I/Os.

Digital electronics

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Digital electronics

Digital electronics - Logic gates

AND, OR, NOT, NAND, NOR, XOR and their truth tables.

Digital electronics - Boolean algebra

Identities, theorems, simplification of logical expressions.

Digital electronics - Sequential logic

D flip-flops, registers, counters, metastability.

Digital electronics - Binary codes

Weighted codes, Gray, Excess-3, parity and Hamming.

Digital electronics - Karnaugh and canonical forms

Minterms, maxterms, Gray adjacency and logic simplification.

Protocols

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Protocols

Protocols - UART

Asynchronous serial link: start bit, data, parity, stop, baud rate.