Zynq PS vs PL: Architecture, AXI, and System Partitioning

Understand the Zynq processing system and programmable logic, how to partition a design between PS and PL, and how both sides communicate over AXI.

What Is a Zynq SoC?

A SoC (System on Chip) combines one or more processors, memory controllers, and peripherals on a single die. A conventional SoC does not necessarily contain programmable logic. A Zynq is an FPGA SoC: it adds an FPGA fabric directly connected to the processor system on the same silicon.

AMD/Xilinx's Zynq-7000 family combines a dual-core ARM Cortex-A9 processor with a 7-series FPGA architecture. Newer families such as Zynq UltraScale+ MPSoC add ARM Cortex-A53 and Cortex-R5 cores while retaining the distinction between the processor system and programmable logic.

Why Use a SoC Instead of a Standalone FPGA?

The main benefit is placing each function where it is most efficient:

the processor runs software, an operating system, network protocols, file systems, and decision-heavy algorithms;
the FPGA handles parallel data streams, custom interfaces, and strict real-time constraints;
integrating both on one die reduces latency, power, board area, and component count compared with separate CPU and FPGA devices;
DDR memory can be shared: software prepares buffers and a hardware accelerator processes them without moving the data over a slow external link.

A Zynq is therefore useful when an application combines a complex software stack with deterministic hardware processing: industrial vision, software-defined radio, robotics, high-speed acquisition, or motor control. If the problem is software-only, a microcontroller may be simpler. If the whole design is a hardware pipeline without advanced software, a standalone FPGA may be enough.

Internal architecture of a Zynq-7000 SoC: Processing System, AXI ports, and Programmable Logic

Overview of a Zynq-7000: the Processing System is in the upper section and the programmable logic is in the lower section.

The Two Sides of Zynq

Processing System (PS)

The PS is a hard-wired processor subsystem. On a Zynq-7000, it includes:

Element	Role
CPU	Two ARM Cortex-A9 cores running software
Caches and internal memory	L1/L2 caches and On-Chip Memory
DDR controller	Access to external DDR without consuming FPGA logic

Requirement	Preferred side
User interface, networking, files, configuration	PS
Sequential algorithm with many branches	PS
Parallel processing of a continuous stream	PL
Custom protocol or nanosecond-level timing	PL
Acceleration of an expensive function	PS for control, PL for computation

Interface	Typical initiator	Use
AXI GP / AXI HPM	PS → PL	Read and write an IP's control registers
AXI GP slave	PL → PS	PL access to the PS address space for moderate-bandwidth needs
AXI HP / HPC	PL → PS and DDR	High-throughput transfers, often using DMA
AXI ACP / ACE / coherent HPC	PL → PS caches	Coherent data sharing with processor caches
EMIO	PS ↔ PL	Route GPIO, UART, SPI, or I2C signals; this is not an AXI bus

// Bare-metal example: AXI-Lite registers of an IP in the PL
Xil_Out32(IP_BASEADDR + CONTROL_OFFSET, START_MASK);
 
while ((Xil_In32(IP_BASEADDR + STATUS_OFFSET) & DONE_MASK) == 0) {
    // The CPU can also wait for an interrupt instead of polling the register.
}

Criterion	Standalone FPGA	Microcontroller	Zynq SoC
Software and OS	Limited without an added processor	Bare metal or RTOS, sometimes Linux	Bare metal, RTOS, or Linux
Deterministic parallelism	Excellent	Limited	Excellent in the PL
High-level peripherals	IP must be integrated	Usually integrated	Integrated in the PS
Design complexity	Hardware	Usually low	Hardware and software
Typical use	Pure hardware pipeline or interface	Mostly software control	Software control plus hardware acceleration

Zynq PS vs PL: Architecture, AXI, and System Partitioning

What Is a Zynq SoC?

Why Use a SoC Instead of a Standalone FPGA?

The Two Sides of Zynq

Processing System (PS)

Programmable Logic (PL)

Partitioning an Application Between PS and PL

PS ↔ PL Communication

Control Path and Data Path

System Boot

Quick Comparison

Key Points to Remember