Chargement…
Chargement…
Short chapter quizzes with maximum XP on the first try and detailed feedback after the correct answer.
Quizzes
36
Done
0
Questions
198
Origins, uses and role of VHDL in the FPGA flow.
Entity, architecture, libraries and ports of a VHDL module.
Telling apart memoryless (combinational) and clocked (sequential) logic.
std_logic, std_logic_vector, integer, unsigned, signed and conversions.
Logical, arithmetic, comparison, concatenation and precedence rules.
Differences between signal, variable and constant: scope, update timing, synthesis.
Naming conventions, code organization and classic pitfalls.
Sensitivity list, sequential vs combinational, latches, process(all).
Three classic ways to write a MUX and what they imply for synthesis.
Picking synthesis and simulation tools depending on the target.
Building a hierarchical design: declaration, instantiation, port map.
Testbench structure, clock generation, stimuli, assertions.
Moore vs Mealy, state encoding, one- or two-process style.
Generate, attributes, advanced generics, packages, conditional generation.
LUTs, flip-flops, BRAMs, DSPs, interconnects and I/Os.
Synthesis, mapping, place, route and bitstream.
Visual IP assembly, VHDL packaging, SoC integration.
Latency, throughput, critical path, registers and temporal verification.
Setup, hold, slack, critical path, timing constraints.
Zynq architecture, PS-PL communication over AXI, embedded design.
SAR ADC, R-2R DAC, comparator and digital sequencing.
AND, OR, NOT, NAND, NOR, XOR and their truth tables.
Identities, theorems, simplification of logical expressions.
D flip-flops, registers, counters, metastability.
Weighted codes, Gray, Excess-3, parity and Hamming.
Minterms, maxterms, Gray adjacency and logic simplification.
PISO/SIPO registers, synchronous counters, modulo counters and terminal-count signals.
Parity, syndrome, Hamming and correction limits.
Asynchronous serial link: start bit, data, parity, stop, baud rate.
Synchronous serial bus: MOSI, MISO, SCLK, CS, modes 0-3.
Two-wire open-drain serial bus, 7-bit addressing, ACK, start and stop.
Open-source SoC bus: master/slave, cycles, handshake.
Intel/Altera bus family: Avalon-MM, Avalon-ST.
ARM AMBA memory-mapped bus: 5 channels, bursts, IDs, VALID/READY handshake.
Simplified AXI variant: single-beat transactions, no bursts, ideal for register access.
AXI streaming variant: single channel, no address, for DSP / video.