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8-bit Register with Enable

Beginner

Simulate (Icarus Verilog)

00:00

Specification

01Operation

The register uses an active-high synchronous reset.

Behavior

On a rising edge, reset=1 clears the register.
Otherwise enable=1 loads data_in; enable=0 retains the value.

02Interface

clk, reset, enable

Direction: Input
Width: 1 bit
Description: Clock and controls

data_in

Direction: Input
Width: 8 bits
Description: Data to load

data_out

Direction: Output
Width: 8 bits
Description: Stored value

← D Flip-flop with Asynchronous Reset