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D Flip-flop with Asynchronous Reset

Beginner

Simulate (Icarus Verilog)

00:00

Specification

01Operation

The flip-flop reacts to the clock and immediately to reset.

Behavior

reset_n=0 immediately forces q=0.
Otherwise, each rising edge of clk copies d into q.

02Interface

clk

Direction: Input
Width: 1 bit
Description: Clock

reset_n

Direction: Input
Width: 1 bit
Description: Active-low asynchronous reset

d

Direction: Input
Width: 1 bit
Description: Data

q

Direction: Output
Width: 1 bit
Description: Stored state

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