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8x4 ROM

Intermediate

Simulate (GHDL)

00:00

Specification

01General Operation

ROM Content:

Address	Data
000	0001
001	0010
010	0100
011	1000
100	1111
101	1010
110	0101
111	1100

02Interface

i_addr

Direction: Input
Width: 3 bits
Description: Address (0 to 7)

o_data

Direction: Output
Width: 4 bits
Description: Data read

← 4-Bit Bidirectional Shift Register