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4-Bit Bidirectional Shift Register

Intermediate

Simulate (GHDL)

00:00

Specification

01General Operation

On rising edge based on i_mode:

00: hold
01: shift right, i_sin enters at MSB
10: shift left, i_sin enters at LSB
11: parallel load from i_data

Reset clears register to "0000".

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: Clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-high async reset

i_mode

Direction: Input
Width: 2 bits
Description: Mode: 00=hold, 01=shift right, 10=shift left, 11=load

i_sin

Direction: Input
Width: 1 bit
Description: Serial input (for shift)

i_data

Direction: Input
Width: 4 bits
Description: Parallel data

o_q

Direction: Output
Width: 4 bits
Description: Register content

← 8-Bit Register with Load Enable