>_FPGA Pour Tous Blog

Blog Careers Challenges Leaderboard Community Certification Projects The Club

Chargement…

>_FPGA Pour Tous

Learn VHDL, from beginner to expert.

Courses

VHDL
Verilog
SystemVerilog
FPGA
Hardware and PCB
Digital Electronics
Protocols
Zynq

Practice

All exercises
HW to simulation
VHDL specifications
Verilog specifications
Software to schematic
Block Design
Testbench
Leaderboard
Report a bug

Blog

FPGA & VHDL articles
Challenges
Certification
Community
FAQ

© 2026 FPGA Pour Tous

FAQ|Legal|Privacy|Terms

8-Bit Register with Load Enable

Intermediate

Simulate (GHDL)

00:00

Specification

01General Operation

On rising edge, if i_load = '1', the register loads i_data. Otherwise it holds. Reset clears to "00000000".

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: Clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-high async reset

i_load

Direction: Input
Width: 1 bit
Description: Parallel load

i_data

Direction: Input
Width: 8 bits
Description: Data to load

o_q

Direction: Output
Width: 8 bits
Description: Register content

← Cascadable N-Bit Comparator