4-Bit SIPO Shift Register

4-bit serial-in parallel-out (SIPO) register. After 4 clock edges, the user has serialised a 4-bit word now available in parallel on o_q.

Behaviour:

• Reset (i_reset='1'): o_q ← "0000".
• Rising edge of i_clk: right shift; i_sin enters at the MSB, the old LSB is dropped.
• o_q is wired combinationally to the 4 flip-flops' current state.

*Asynchronous active-high reset.*