4-Bit Left Shift Register

4-bit left shift register. Bits advance one position to the left on each clock cycle.

Behaviour:

• Reset (i_reset='1'): o_q ← "0000" and, consequently, o_sout ← '0'.
• Rising edge of i_clk: shift left, with i_sin inserted into the LSB.
• o_q continuously reflects the four flip-flop states.
• o_sout continuously reflects the current MSB, i.e. o_q(3). It does not store the bit shifted out at the preceding edge.

*Asynchronous active-high reset.*