4-Bit SAR ADC Controller

The controller starts when i_start='1' and o_ready='1'. It tests bits from most significant to least significant. On each cycle, i_cmp='1' means the input voltage is greater than or equal to the current DAC value: the tested bit is kept. Otherwise, the tested bit is cleared.

Behaviour

• conversion over 4 cycles after start;
• o_dac_code exposes the current trial word;
• o_valid becomes '1' when o_result contains the final result;
• synchronous active-high reset.