SHA-256 core (1-block)

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Specification

01General operation

The SHA-256 core hashes a single 512-bit block presented in parallel as 16 words of 32 bits (i_msg0..i_msg15). The computation starts on a i_gen_hash='1' pulse. After ~68 clock cycles, o_ready goes to '1' and o_hash (256 bits) holds the result.

The design follows FIPS 180-4:

64 rounds of compression on 8 working registers a..h (32 bits each)
A 16-word shift register implements the message schedule W_i for the last 48 rounds
ROM c_K stores the 64 round constants
At block end, the 8 state registers H0..H7 are added to the compression outputs a..h to produce the final hash.

02Top-level interface

i_clk

Direction: Input
Width: 1 bit
Description: Clock

i_rst

Direction: Input
Width: 1 bit
Description: Active-high reset: asynchronous for controller state, synchronous for pipeline registers and H0..H7 IVs

i_gen_hash

Direction: Input
Width: 1 bit
Description: Start pulse (>= 1 cycle)

i_msg0..i_msg15

Direction: Input
Width: 16 * 32 bits
Description: 512-bit block (msg_15 = first bytes, msg_0 = bit length)

o_ready

Direction: Output
Width: 1 bit
Description: '1' when o_hash is valid

o_hash

Direction: Output
Width: 256 bits
Description: SHA-256 digest (H0 MSB, H7 LSB)

03sha256_core FSM

States: ST_IDLE, ST_INIT, ST_RUN, ST_M1..ST_M15, ST_WS.

IDLE: wait for i_gen_hash. On start, pulse w_gen_p (fed into the delay pipeline) and reset r_cnt.
INIT: synchronous reset of msg_comp (w_rst_cmp='1'), counter starts.
RUN..M15: for 16 cycles, drive w_m = i_msg15, i_msg14, ..., i_msg0 into the i_w input of msg_comp. In ST_M15, assert w_rst_sch='1' to freeze the schedule.
WS: for the next 48 rounds, w_m takes the w_w_j value produced by the schedule. Leave when r_delay(66)='1'.

Counter: r_cnt increments while w_start='1', selecting c_K(to_integer(r_cnt)) (synchronous read -> K_i delayed by one cycle, aligned with msg_comp).

04Delay pipeline and H0..H7

A 67-stage flip-flop pipeline (r_delay(0..66)) propagates the w_gen_p pulse. Its depth matches the combined latency of the schedule and compression.

r_delay(65)='1' is the final-add signal. P_FINAL then adds a..h to variables v_h0..v_h7, initialised to the FIPS IV on i_rst:

- H0 = 6a09e667, H1 = bb67ae85, H2 = 3c6ef372, H3 = a54ff53a

- H4 = 510e527f, H5 = 9b05688c, H6 = 1f83d9ab, H7 = 5be0cd19

r_delay(66) is both the o_ready output and the FSM return-to-IDLE trigger.

05Testbench

The testbench applies the ASCII string "test" (4 bytes) with FIPS 180-4 padding:

msg_15 = 0x74657374 (the 4 bytes of "test")
msg_14 = 0x80000000 (pad bit and zeros)
msg_13..msg_1 = 0
msg_0 = 0x00000020 (length = 32 bits)

The TB checks o_ready, then the 8 words of the expected digest:

9f86d081 884c7d65 9a2feaa0 c55ad015 a3bf4f1b 2b0b822c d15d6c15 b0f00a08.

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