Reading a Complete Small RTL Design

Review a packet counter from its interface through corner cases, then connect the code to expected hardware.

The requirement

The following module receives a stream with valid, ready, data, and last. It adds the bytes in one packet. On transfer of the last byte, it publishes the sum and raises o_sum_valid for one cycle.

A transfer occurs only when i_valid && o_ready is 1 on a rising edge. The module can accept one byte every cycle.

module packet_sum #(
  parameter int unsigned DATA_WIDTH = 8,
  parameter int unsigned SUM_WIDTH  = 16
) (
  input  logic                  i_clk,
  input  logic                  i_rst,
  input  logic                  i_valid,
  output logic                  o_ready,