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16 x 8 Synchronous-read RAM

Intermediate

Simulate (Icarus Verilog)

00:00

Specification

01Operation

Output data corresponds to the address sampled on the last edge.

Behavior

A valid write updates the addressed location.
At each edge, data_out takes the value at the read address.

02Interface

clk, write_enable

Direction: Input
Width: 1 bit
Description: Clock and write control

write_address, read_address

Direction: Input
Width: 4 bits
Description: Write and read addresses

data_in

Direction: Input
Width: 8 bits
Description: Write data

data_out

Direction: Output
Width: 8 bits
Description: Registered read data

← 16 x 8 Asynchronous-read RAM