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4-bit Up-down Counter

Intermediate

Simulate (Icarus Verilog)

00:00

Specification

01Operation

Direction is sampled only while counting is enabled.

Behavior

up=1 increments and up=0 decrements when enable=1.
reset=1 synchronously clears the counter.

02Interface

clk, reset, enable, up

Direction: Input
Width: 1 bit
Description: Clock and controls

count

Direction: Output
Width: 4 bits
Description: Current value

← Parameterized Counter